1. Field of Invention
This invention relates to communication devices. More particularly, the invention relates to communication interfaces between Media Access (MAC) and Physical (PHY) layers in Open System Interconnection (OSI) architecture.
2. Description of Prior Art
To communicate between MAC and PHY layers, a data interface is defined. The interface definition is sometimes determined by standards, but is more often determined by hardware developers as a matter of convenience. For example, the IEEE 802.14 Standard for Cable-TV Based Broadband Communication Network being developed through the Institute of Electrical and Electronic Engineers, has proposed numerous proposals for lower level protocols including the MAC and PHY layers. As a result an Application Specific Integrated Circuit (AISC) developed for a particular protocol may be obsolete when a new PHY interface is defined. The ASIC redesign tends to be costly, time-consuming and delays the introduction of PHY hardware improvements. Accordingly, a need exists for a data interface which can be programmed to serve a wide variety of PHY layer interface implementations without redesign of the interface and related ASIC devices.
Prior art related to data interfaces includes the following: U.S. Pat. No. 5,243,273 issued Sep. 7, 1993, discloses a general purpose, reconfigurable system for processing serial bit streams. The system contains one or more reconfigurable bit processors which maybe connected together in a building block fashion to perform low-level processing on serial data received from or sent to a personality module. One of a plurality of serial test sequences receives or sends data from/to the reconfigurable bit processor; provides a user programmable means to control the application and reception of test patterns to and from a channel; and interfaces to the user through a system controller.
U.S. Pat. No. 5,365,546 issued Nov. 15, 1994, discloses an interface device including a programmable memory for storing a number of reference values which allow the interface device to be configured to normalize data signals and control sequences in accordance with operating characteristics of any one of a number of available transceiver modules. The stored reference value control timing sequences for initiating and shutting down a transmit cycle, for storing predetermined maximum deviation values for the modulation bias signal of transmitted data messages, and for demodulating received signals.
U.S. Pat. No. 5,459,453 issued Oct. 17, 1995, discloses an interface connector device for interconnecting a plurality of input/output devices including a signal bus connected to a control and to the input/output devices for multiplexing the signals between the control and the input and output devices. Each of the interface and connector devices includes address recognition circuitry as well as programmable configuration selection logic to configure the connector device to respond to a variety of input/output devices. The signal bus and connector devices are further adapted to recognize and convey various levels of signals, for example, different voltages levels representing control information, framing signals, and diagnostic command signals.
U.S. Pat. No. 5,465,106 issued Nov. 7, 1995, discloses a generic driver interface including a configurable digital circuit card that has programmable logic functions and I/O connectors to provide the capability of implementing many new or old circuit designs without re-etching the circuit card. The circuit card utilizes a programmable gate array, bi-directional programmable I/O driver, and an EEPROM to provide for reconfiguration of the circuit card upon reset. The logic functions and I/O pins of the circuit card are programmable to allow emulation of old designs and implementation of a new design without the need to physically modify the card. The configuration program of the circuit card is stored in the EEPROM which has edge-programmability to eliminate the need of removing the EEPROM prior to programming.
U.S. Pat. No. 5,473,758 issued Dec. 5, 1995, discloses a microcontroller device adapted to be programmed using digital command words or other bit patterns applied as inputs after installation of the device in a circuit. The system is controlled by the device to have its programming pins isolated from the system to avoid effects on system operation while the programming is taking place. A serial/parallel programming interface between the pins and the program memory enables shifting of output pins between programming mode and normal mode without dedicating input/output pins for programming mode.
U.S. Pat. No. 5,519,701 issued May 21, 1996, discloses a programmable interface for defining and dynamically configuring a multiple circuit FIFO storage means to include other parameters useful in the management of data transferred between a host bus and a network.
U.S. Pat. No. 5,604,870 issued Feb. 18, 1997, discloses an interface device for coupling a peripheral controller to a host computer. The interface device includes an emulated Universal Asynchronous Receiver/Transmitter (UART) to take advantage of existing host operating systems arranged to accept and communicate with a PCMCIA compatible or other compliant peripheral function without sacrificing physical space, material cost or functionality of the peripheral function.
U.S. Pat. No. 5,111,423 issued May 5, 1992, discloses a programmable interface for use between a communication bus in a computer system and a peripheral circuit in the computer system. The peripheral circuit card has configuration registers for indicating to the communication system via the communication bus various characteristics of the circuit card. The programmable interface may be customized by the user for any particular peripheral circuit card design.
U.S. Pat. No. 5,371,736 issued Dec. 6, 1994, discloses a universal protocol communications interface which can be either reconfigured or reprogrammed to handle communications among communication devices operating under a variety of different bit-oriented communication protocols.
U.S. Pat. No. 5,617,040 issued Apr. 1, 1997, discloses an integrated circuit with programmable output drive/program pads. The output drive/program pads are programmed by either connecting a resistor from one of the output paths to a positive voltage rail or to a negative voltage rail or by allowing the node to float. Accordingly, a three state programming input is realized in a programming mode.
U.S. Pat. No. 5,615,344 issued Mar. 25, 1997, and having a filing date of Nov. 12, 1992, discloses a reconfigurable interface circuit between a peripheral device and a computer device which reconfigures an interface bus according to a flexibly defined signal between the computer and the peripheral device. The interface further includes means for providing device specific information to reconfigure the reconfigurable interface circuit and to provide the peripheral device interface circuit.
IBM Technical Disclosure Bulletin, Vol 27, No. 10B, March 1995, pages 6323-4 discloses a technique for interfacing a Programmable Communications Processor (PCP) to a host processing system to increase the flexibility and versatility of host systems requiring compatibility with many communication protocols such as SDLS, HDLC, etc. The PCP may be programmed with the desired communication protocol thereby freeing the host system for higher level activities.
None of the prior art, alone or in combination, show or suggest a programmable output interface in an Open System Interconnection (OSI) architecture for a Cable-TV Broadbased Communication Network which enables a MAC layer to access a variety of PHY layer implementations without redesign of the interface and the related ASIC device.